When computer processors are operating out of a virtual memory, virtual memory addresses (VMAs) are mapped to physical memory addresses (PMAs) to enable memory operations to be performed on a main (physical) memory. A page table may be stored in a known portion of the physical memory and may contain entries mapping VMAs to PMAs for the various processes running on the processor. The page table may store entries on a per-page basis, e.g., in 4 KB pages. However, since accessing the page table can still be time consuming, a computing device may include a translation lookaside buffer (TLB) that is closer to the processor than the main memory and comprises a smaller cache to store entries mapping the VMAs to PMAs for a number of memory pages. For example, a memory management unit (MMU) may handle memory access requests for a processor, and may first search the TLB for an entry mapping a VMA to a PMA for a memory access request before searching the page table, which may be referred to as a “page walk.” The size of the TLB may be selected based upon a tradeoff between how much memory can be simultaneously mapped in the TLB and how long it takes to scan the TLB. For example, TLBs are often between 64-4096 entries, with a typical TLB size of 256 entries, which corresponds to only 1 MB of virtual memory when utilizing a page size of 4 KB.